1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device whose internal state is set in accordance with a type of an external device via an external pin.
2. Description of the Related Art
A semiconductor device to which a plurality of types of external devices are connectable is provided with an internal circuit (external interface circuit) which controls the external devices. In order to set an operation mode of the internal circuit in accordance with the type of the external devices, the following signal transmitting methods and the like are adopted: one method is that a selector selects a desired control parameter signal from a plurality of control parameter signals according to a level value of an external input signal and transmits the selected control parameter signal to the internal circuit; and another method is that according to a level value of an external input signal, a CPU writes a data signal to a control parameter setting register, which then transmits a desired control parameter signal to the internal circuit.
FIG. 1A and FIG. 1B show a conventional semiconductor device (a first conventional example). FIG. 1A shows the structure of a semiconductor device of the first conventional example. In a semiconductor device 100 of the first conventional example, a selector 102 selects one of control parameter signals CO1˜COi according to a level value of each of a plurality of external input signals E that are supplied thereto via a plurality of external pins PA, and outputs the selected signal as a control parameter signal C. For example, in response to the activation of a reset signal /RST (not shown), level values of the control parameter signals CO1˜COi are set to level values determined for the respective control parameter signals CO1˜Coi in advance. Incidentally, the reset signal /RST is a signal that is activated when the semiconductor device 100 is reset. An internal circuit 104 executes an operation of outputting an external control signal CTL via an external pin PB according to a level value of the control parameter signal C supplied thereto from the selector 102. For example, the internal circuit 104 handles the external control signal CTL as a positive logic signal when the level value of the control parameter signal C is “0”, whereas it handles the external control signal CTL as a negative logic signal when the level value of the control parameter signal C is “1”.
FIG. 1B shows the operation in the semiconductor device in FIG. 1A when it is reset. It is assumed here that the level value of the control parameter signal CO1 is set to “1” in response to the activation of the reset signal /RST. It is also assumed that an external device externally attached to the semiconductor device 100 is of a type that handles the external control signal CTL as a negative logic signal. Accordingly, it is assumed that the level value of the external input signal E has been set to a level value based on which the selector 102 selects the control parameter signal CO1. In such a case, when a level value of the reset signal /RST changes from “1” to “0” (when the reset signal /RST is activated), the level value of the control parameter signal CO1 is initialized to “1”, and since the control parameter signal CO1 has been selected by the selector 102, the level value of the control parameter signal C is initialized to “1”. Consequently, from an instant immediately after the semiconductor device 100 is reset, the internal circuit 104 handles the external control signal CTL as the negative logic signal to set a level value of the external control signal CTL to “1”.
FIG. 2A and FIG. 2B show a conventional semiconductor device (second conventional example). FIG. 2A shows the structure of the semiconductor device of the second conventional example. In a semiconductor device 200 of the second conventional example, after the semiconductor 200 is reset, a CPU 202 writes a data signal D to a register 204 according to a level value of each of a plurality of external input signals E supplied thereto via a plurality of external pins PA. The register 204 constantly sets a level value of a control parameter signal C, which is to be supplied to the internal circuit 206, equal to a register value. The register value of the register 204 is initialized to a predetermined value (for example, “0”) in response to the activation of a reset signal /RST. Incidentally, the reset signal /RST is a signal that is activated when the semiconductor device 200 is reset. The internal circuit 206 executes an operation of outputting an external control signal CTL via an external pin PB according to the level value of the control parameter signal C supplied thereto from the register 204. For example, similarly to the internal circuit 104 in FIG. 1A, the internal circuit 206 handles the external control signal CTL as a positive logic signal when the level value of the control parameter signal C is “0”, whereas it handles the external control signal CTL as a negative logic signal when the level value of the control parameter signal C is “1”.
FIG. 2B shows the operation in the semiconductor device in FIG. 2A when it is reset. It is assumed here that an external device externally attached to the semiconductor device 200 is of a type handling the external control signal CTL as the negative logic signal. Accordingly, it is assumed that the level value of the external input signal E has been set to a level value based on which the CPU 202 writes the data signal D (“1”) to the register 204. In such a case, when a level value of the reset signal /RST changes from “1” to “0” (when the reset signal /RST is activated), the register value of the register 204 is initialized to “0”, so that the level value of the control parameter signal C is initialized to “0”. Consequently, immediately after the semiconductor device 200 is reset, the internal circuit 206 handles the external control signal CTL as the positive logic signal and the level value of the external control signal CTL is set to “0”. Thereafter, when the CPU 202 writes the data signal D (“1”) to the register 204, the level value of the control parameter signal C is changed from “0” to “1”. Therefore, from an instant when the CPU 202 writes the data signal D (“1”) to the register 204, the internal circuit 206 handles the external control signal CTL as the negative logic signal to set the level value of the external control signal CTL to “1”.
Further, Japanese Unexamined Patent Application Publication No. Hei 7-6154 discloses an art to realize an effective use of external pins without reducing the number of general-purpose external pins by making a plurality of operation modes settable in a microcomputer via one external pin dedicated for operation mode setting. Specifically, at a resetting of the microcomputer, a signal inputted from the general-purpose external pin is latched in response to a signal inputted from a reset external pin, and the latched signal and a signal inputted from the external pin dedicated for operation mode setting are decoded, whereby an operation mode setting signal corresponding to a result of the decoding is selected from a plurality of operation mode setting signals. Japanese Unexamined Patent Application Publication No. Sho 60-31641 discloses an art to realize simplification of an external circuit and easy-to-use structure thereof for a user by making switchable a mode designated by a user and a mode set from an exterior via one external pin in a one-chip microcomputer.
In the first conventional example shown in FIG. 1A and FIG. 1B, immediately after the resetting of the semiconductor device 100, the level value of the external input signal E is reflected in the level value of the control parameter signal C, and the internal circuit 104 executes a desired operation (handles the external control signal CTL as the negative logic signal). However, there is a drawback of less versatility since the level value of the control parameter signal C cannot be changed after the semiconductor device 10 is reset.
On the other hand, in the second conventional example shown in FIG. 2A and FIG. 2B, after the semiconductor device 200 is reset, the level value of the control parameter signal C is changeable by the CPU 202 writing the data signal D to the register 204. However, a drawback of this example is that the internal circuit 206 executes an undesired operation (handles the external control signal CTL as the positive logic signal) during a period from the instant immediately after the semiconductor 200 is reset to a instant when the CPU 202 writes the data signal D to the register 204, since the level value of the external input signal E is not reflected in the level value of the control parameter signal C from the instant immediately after the semiconductor device 200 is reset.